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Huawei's Ascend 960DT NPU lands early to challenge Nvidia in China

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Huawei's Ascend 960DT NPU lands early to challenge Nvidia in China

At its annual Connect conference, Huawei unveiled a new generation of AI accelerators it says outperforms anything Nvidia can currently sell inside China. The flagship, the Ascend 960DT, is arriving a full three quarters ahead of schedule: Huawei now plans to launch it in the first quarter of 2027 rather than later. The chip offers up to 288 GB of what The Register assumes is Huawei's custom HiZQ memory, a homegrown substitute for high-bandwidth memory, plus up to 4 petaFLOPS of FP4 performance (half that at FP8). That is twice the performance and memory of Huawei's own 950-series parts launched earlier this year. Against the Nvidia hardware China is actually allowed to buy, the B300 family, the 960DT matches memory and bandwidth but delivers only about half the FP8 compute and a third the FP4 compute. It remains well behind Nvidia's unreleased-in-China Rubin and AMD's MI455X, which promise 35 to 50 petaFLOPS of FP4, 288 GB of HBM4 memory and 22 TB/s of bandwidth. Huawei is compensating with scale rather than raw chip density: using near-packaged optics (NPO) interconnects, it can link up to 4,096 Ascend 960-series chips into a single compute domain delivering up to 16 exaFLOPS of FP4 compute, comparable to how Nvidia and AMD scale rack-scale systems from 72 GPUs up to 576 via optical interconnects. Huawei says its Hi-One NPO units let it consolidate 48,000 800 Gbps optical pluggables into 5,500 NPO units, cutting power draw by 550 kilowatts, halving failure rates, and reaching 99.8 percent uptime, addressing a reliability problem in earlier Huawei designs that reportedly forced DeepSeek to abandon Huawei NPUs for training and switch back to Nvidia GPUs. Alongside the 960DT, Huawei is preparing a compute-optimized companion chip, the 960PR, for Q3 2027: it trades memory and bandwidth (192 GB of custom HiBL memory at 2.4 TB/s, versus the 960DT's larger pool) for up to 8 petaFLOPS of FP4 compute, and is designed to handle the compute-heavy prefill stage of LLM inference while the 960DT handles the memory-heavy decode stage, a heterogeneous split similar to Nvidia's Vera Rubin/Rubin CPX pairing before Nvidia canceled Rubin CPX. At Connect, Huawei also said it intends to scale compute clusters to half a million or more NPUs, demonstrating a proof of concept in which an Ascend 950-based TaiShan superpod scaled to 4,096 accelerators; the company expects a two-tier, four-plane Clos network topology to support up to 512,000 NPUs soon, with a multi-rail topology eventually enabling million-NPU superclusters. The Register notes this remains a theoretical configuration Huawei has not yet proven in production. Further out, Huawei teased the Ascend 970-series for 2028, targeting up to 3.6 petaFLOPS FP8 or 14 petaFLOPS FP4 with memory bandwidth rising to 14.4 TB/s while capacity stays near 288 GB, and a following generation by 2029 aiming to double performance again to 7.2 petaFLOPS FP8 and 28 petaFLOPS FP4, with 384 GB of memory and 38.4 TB/s of bandwidth.

Key facts

  • The Ascend 960DT now launches in Q1 2027, three quarters ahead of schedule, with up to 4 petaFLOPS FP4 (half that at FP8), 288 GB of custom HiZQ memory, and double the performance and memory of Huawei's 950-series.
  • Against Nvidia's China-legal B300 chips, the 960DT matches memory and bandwidth but has only about half the FP8 and a third the FP4 compute; it trails Nvidia's Rubin and AMD's MI455X (35-50 petaFLOPS FP4, 288 GB HBM4, 22 TB/s) by a wide margin.
  • Huawei's near-packaged optics interconnect links up to 4,096 chips into one 16-exaFLOPS FP4 domain, and Huawei says consolidating 48,000 optical pluggables into 5,500 Hi-One NPO units cut power use by 550 kW, halved failure rates, and lifted uptime to 99.8 percent.
  • A companion chip, the Ascend 960PR (Q3 2027), delivers up to 8 petaFLOPS FP4 with 192 GB of HiBL memory at 2.4 TB/s and is designed to run inference prefill alongside the 960DT's decode workload.
  • Huawei says it aims for clusters of half a million or more NPUs, after scaling a 950-based TaiShan superpod to 4,096 accelerators as proof of concept; The Register flags the larger cluster sizes as still theoretical.

Why it matters

Export restrictions keep Nvidia's and AMD's best accelerators out of China, so the ceiling for Chinese AI development is set by whatever Huawei can ship domestically. Pulling the Ascend 960DT's launch forward by three quarters and pairing it with a purpose-built interconnect signals Huawei is racing to close that ceiling faster than its own roadmap once assumed, at a moment when Chinese developers have limited alternatives.

Who it affects

Chinese AI labs and cloud operators building on domestic hardware are the direct audience: the article notes DeepSeek reportedly had to abandon earlier Huawei NPUs for training and fall back to Nvidia GPUs, which is exactly the kind of reliability problem Huawei says its new optical interconnect tech now addresses. It also matters to Nvidia and AMD, whose China-legal chips (like the B300) are the actual benchmark Huawei is closing in on, not their unrestricted flagship parts.

How to use it

The Ascend 960DT is scheduled for Q1 2027, with the compute-optimized 960PR following in Q3 2027; the two are meant to be deployed together, with the 960PR handling the compute-heavy prefill phase of LLM inference and the 960DT handling the memory-heavy decode phase. Huawei's NPO interconnect lets developers scale a single compute domain to as many as 4,096 chips today, with larger clusters positioned as a near-term roadmap item rather than something available now.

How solid is it

The figures come from Huawei's own presentation at its Connect conference, reported by The Register's Tobias Mann without a named Huawei spokesperson quoted directly; all claims are attributed to "Huawei says" or "Huawei claims." Chip specs and comparisons against Nvidia and AMD parts are stated as vendor figures rather than independently benchmarked, and the article itself flags the largest cluster-size claims as unproven.

Risks and caveats

The headline comparisons favor Huawei only against the cut-down Nvidia chips actually sold in China; against Nvidia's Rubin and AMD's MI455X, the 960DT still trails substantially in raw compute. The 512,000-NPU and million-NPU cluster figures are explicitly described as theoretical, not something Huawei has deployed. No pricing, cost or export-availability details are given for any of the chips, and the roadmap stretches out to 2029, leaving three years in which Huawei's own plans could change.