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Nvidia outlines CUDA support requirements for RISC-V

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Nvidia outlines CUDA support requirements for RISC-V

At Hot Chips 2026, Nvidia presented the requirements a RISC-V CPU and platform must meet to run CUDA, its software layer for GPU compute that today supports only x86-64 and aarch64 processors. The talk, covered by Chester Lam at Chips and Cheese, set a high bar: Nvidia wants an RVA23-profile CPU that also complies with RISC-V's server SoC and server platform specifications, which bring reliability, availability and serviceability (RAS) features and a dedicated security processor. Nvidia added requirements beyond those specs because it did not want CUDA stuck supporting a lowest common denominator of hardware: it needs vector extensions so it can use predication instead of branches, and it needs ACPI so software can discover what the hardware supports for power, performance and thermal management. ACPI was a sticking point until 2025, when the UEFI Forum added RISC-V ACPI support and the RISC-V BRS (Boot and Runtime Services) specification, which includes ACPI, was ratified.

Two more requirements round out the list. Nvidia wants guaranteed PCIe coherency: without it, a CPU that has just written data to a cache could see the GPU's DMA engine read stale data from DRAM instead, and software would have to insert explicit cache invalidations to avoid the mismatch, something Nvidia does not want built into the CUDA stack. RISC-V's server SoC specification only recommends cache coherency; Nvidia is asking for a guarantee. Nvidia also wants peer-to-peer PCIe communication support, so data moving between two devices does not have to detour through CPU memory. Nvidia did not itemize every requirement in the talk, saying only that the full list fits within two pages and targets an unspecified 'certain level of performance.'

Nvidia also covered NVLink Fusion, a program that lets other companies license its NVLink interconnect IP for use with a custom CPU of their choice, RISC-V included. A product built this way would resemble Nvidia's GB10, which links a MediaTek CPU die to an Nvidia GPU over NVLink C2C. NVLink Fusion requires everything CUDA does, plus support for Nvidia's DOCA and NCCL software frameworks and what Nvidia calls a close partnership, comparable to its cooperation with MediaTek on GB10.

Lam's own assessment is that the RISC-V software ecosystem still lags x86-64 and aarch64, and that almost no RISC-V hardware on the market today meets Nvidia's bar; he says he would be surprised if any consumer RISC-V hardware qualifies soon. ACPI is the requirement he flags as hardest to clear: adoption has been inconsistent even in the more mature aarch64 world, and the RISC-V version of the standard, ratified only in 2025, will likely take years to see broad support. The first CUDA-capable RISC-V systems, he expects, will be server hardware rather than the single-board computers hobbyists use. Nvidia named SiFive as a partner and said SiFive plans to demo a CUDA-capable RISC-V system at Hot Chips; Nvidia implied the example CPU specifications on its slide match that system, which point to a high-core-count server chip. Lam argues the missing pieces do not have to be dealbreakers: predictable branches can substitute for predication, and the performance cost of software cache invalidation may be acceptable for workloads where computation dominates data movement, with the same logic applying to PCIe peer-to-peer transfers. He says he hopes Nvidia's current requirements reflect the constraints of a fast, low-risk initial port rather than a permanent bar, and that CUDA eventually reaches a wider range of RISC-V systems rather than only specialized server designs.

Key facts

  • Nvidia says a RISC-V CPU must be RVA23-profile and meet RISC-V's server SoC and server platform specifications, which bring RAS features and a dedicated security processor, before it can run CUDA.
  • Beyond those specs, Nvidia also requires vector extensions, ACPI support, guaranteed PCIe coherency and peer-to-peer PCIe communication; ACPI became viable only after the RISC-V BRS specification, which includes it, was ratified in 2025.
  • Nvidia did not detail every requirement, saying only that the full list fits within two pages and targets an unspecified 'certain level of performance.'
  • Nvidia named SiFive as a partner planning to demo a CUDA-capable RISC-V system at Hot Chips; the example specifications Nvidia showed point to a high-core-count server chip, not hobbyist hardware.
  • NVLink Fusion, which lets other companies license Nvidia's NVLink IP for a custom CPU including a RISC-V one, requires everything CUDA does plus support for Nvidia's DOCA and NCCL frameworks and a close partnership comparable to MediaTek's role in the GB10 product.

Why it matters

CUDA currently runs only on x86-64 and aarch64 host CPUs, so a credible path to RISC-V would give server and AI infrastructure builders a third option for the CPU that feeds an Nvidia GPU. Coming from Nvidia itself, at a major hardware conference, the requirements list is a concrete signal that a leading GPU vendor now treats RISC-V as viable for server-class AI compute rather than only for embedded and microcontroller use.

Who it affects

RISC-V CPU and platform vendors chasing the server and AI market, starting with SiFive, whom Nvidia named as its partner. Other chipmakers eyeing the NVLink Fusion path to pair a custom CPU with an Nvidia GPU, the way MediaTek did for GB10. Datacenter and AI infrastructure buyers who would eventually gain another host-CPU option. RISC-V International and the UEFI Forum, whose specifications (server SoC, server platform, BRS/ACPI) are now on Nvidia's checklist. Hobbyists running RISC-V single-board computers are explicitly not the near-term audience.

How to use it

Nothing ships yet: this is a requirements list, not hardware or a driver release. A vendor chasing CUDA compatibility needs an RVA23-profile core, compliance with RISC-V's server SoC and platform specifications, vector extensions, ACPI (available since the RISC-V BRS specification's 2025 ratification), guaranteed PCIe coherency and peer-to-peer PCIe support. A vendor chasing NVLink Fusion licensing needs all of that plus support for DOCA and NCCL and a close working relationship with Nvidia. SiFive's promised demo at Hot Chips is the closest thing to a working example so far.

How solid is it

This is first-hand coverage of an Nvidia conference talk at Hot Chips 2026, so the stated requirements are reliably reported, and Chester Lam clearly marks his own interpretation as his own. What is soft: Nvidia did not itemize its full requirements list, saying only that it fits within two pages and targets 'a certain level of performance' without naming a benchmark; the talk gave no timeline for when compliant RISC-V systems, including SiFive's, will actually ship; and SiFive's Hot Chips demo is described as planned rather than confirmed to have taken place.

Risks and caveats

The bar is steep enough that, per Lam, the vast majority of existing RISC-V hardware fails it today, and he doubts any consumer RISC-V board will qualify soon. ACPI looks like the likely bottleneck: even aarch64, a far more mature platform, has had patchy ACPI support for years, and the RISC-V version of the standard only arrived in 2025. Expect early CUDA-on-RISC-V hardware to be server-grade rather than the cheap boards hobbyists use, and treat Nvidia's current requirements as a starting point that may or may not loosen as the ecosystem matures.

“The vast majority of existing RISC-V hardware won’t meet Nvidia’s requirements.”

— Chester Lam, Chips and Cheese