Glonce

NVIDIA's Vera whitepaper overstates its lead over x86 rivals

infrastructureThe Glonce editorsHacker News🔥67Glonce rating67Impact60Novelty45Relevance70Surprise55Players75Credibility80
NVIDIA's Vera whitepaper overstates its lead over x86 rivals

NVIDIA published a 45-page whitepaper on July 21 introducing Vera, its first server CPU, built around a new in-house core called Olympus. Chips and Cheese, in an article by editor in chief George Cozma and Chester Lam published August 5, argues the underlying hardware looks genuinely strong on independent evidence, but that large stretches of the whitepaper turn straightforward design choices into a 'morality play about x86': traditional simultaneous multithreading (SMT) is drawn as wasteful time-slicing, a configurable NUMA topology is presented as an unavoidable 32-node maze, four standard SPEC benchmarks become 'agentic benchmarks,' undefined performance-counter ratios stand in for causal proof, and an unlabeled pictogram becomes a 1.8x reinforcement-learning result.

On the hardware itself, Vera packs an 88-core monolithic compute die. Each Olympus core is a 10-wide Arm v9.2 design with a neural branch predictor, value prediction, memory renaming, a large instruction window, six 128-bit SVE pipes, four load pipes and two store pipes, a 96 KB L1 data cache, and about 10-cycle access to a 2 MB private L2; the 88 cores share a 3.4 TB/s coherency fabric and 164 MB of distributed last-level cache. The memory subsystem pairs eight SOCAMM2 LPDDR5X modules for up to 1.5 TB of capacity and 1.2 TB/s of bandwidth, which NVIDIA says draws only about 50 watts when populated. The authors credit value prediction as one of Olympus's more distinctive features, used by Apple's cores and, in a narrower form covering only some floating-point instructions, by AMD's Zen 1 and Zen 2 chips, with Olympus's version looking broader and closer to Apple's. But they note the graph prefetcher echoes Intel's Data-Dependent Prefetcher, shipping since 2022, and its Granite Rapids Array of Pointers prefetcher, while the 'neural branch predictor' revives an idea AMD used in 2012's Piledriver and in Zen 1, before shifting from Zen 2 onward to a perceptron predictor that only sets initial direction, overridden by a TAGE predictor for a 30% cut in mispredictions, a shift AMD has likely completed by Zen 5.

Independent testing backs the hardware claims. In May, Phoronix's Michael Larabel benchmarked an early Vera system against current Arm and x86 servers, within a scope NVIDIA controlled: NVIDIA chose the permitted workloads and disallowed frequency or power monitoring, on pre-production hardware tested for one day. Even so, Vera's geometric mean score came in 10% above a 5 GHz EPYC 9575F, 1.55x a Xeon 6980P, and 1.63x Grace, making it, per the authors, the most performant Arm server CPU seen in public testing so far. That result, they write, is strong enough to reject the idea that NVIDIA's whitepaper charts are pure fantasy: Olympus really does appear to be a fast core, which leaves the separate question of whether the whitepaper proves what NVIDIA says it proves.

The first technical problem the authors identify is Figure 5, which contrasts 'Traditional SMT (x86),' drawn as pipeline stages alternating between two threads, with NVIDIA's own 'Spatial Multithreading,' shown as resources statically partitioned between Vera's two hardware threads to avoid what NVIDIA calls 'opportunistic time-sharing.' The authors say this misrepresents how SMT actually works: fetch, decode and allocate do serve one thread per cycle, but execute and memory access are thread-agnostic and can service both threads' operations in the same cycle, so resources are not left idle the way NVIDIA's diagram implies; static partitioning, by contrast, can leave a busy thread unable to use execution resources reserved for an idle sibling. NVIDIA's own text does not actually claim a performance edge for Spatial Multithreading, citing only 'determinism, isolation, and quality of service,' which the authors accept may matter more than throughput for NVIDIA's target market; their objection is to the diagram's misleading impression, not necessarily to the design itself. They separately note that an Olympus core takes 10,000 cycles to revert to single-thread mode once its sibling thread finishes, a switch-back penalty software will need to account for.

The second critique targets NVIDIA's claim that a large two-socket x86 system can expose 'as many as 32 NUMA domains' against Vera's one domain per socket. The 32-domain figure is real but sits at the most fine-grained end of a configurable range; AMD's tuning guide offers NPS4, NPS2, NPS1 and NPS0 modes plus an optional setting that exposes each cache domain separately, not a fixed default. The authors argue an OS-visible NUMA node is an abstraction: Vera still has 88 cores, distributed cache and home nodes, and a packet-switched coherency fabric spread across a large die, so a flatter software topology can make distances more consistent without making them disappear. They also fault the whitepaper's core-to-core latency heatmap for giving no core identities, no minimum, median or maximum figures, and no measurement procedure, so its 'up to 50% lower' headline reflects NVIDIA's best case rather than typical behavior.

NVIDIA labels four standard SPEC CPU 2026 integer workloads, CPython, GCC, LLVM and Cppcheck, as 'agentic benchmarks,' even though SPEC itself describes them as a Python interpreter, two optimizing compilers and a C/C++ static analyzer. The authors note none of them are actually agents: no model serves tokens, no agent runtime chooses tools, and no sandbox starts, blocks on I/O, retrieves context or feeds observations back into a policy. They do credit the paper for correctly labeling the SPEC results as estimates, since production Vera hardware was not yet available. Figure 15 shows a 1.7x to 1.8x per-core advantage on those four tests in a fully loaded two-socket system, but the full SPECrate 2026 Integer Base totals given elsewhere are 925 for two Vera sockets against 898 for two EPYC 9755 sockets, a 3.0% system-throughput edge; both figures hold at once because Vera's system uses 176 physical cores against EPYC's 256, so per core Vera runs about 50% faster across the full suite and 70 to 80% faster on the four selected tests. A separate chart, Figure 19, is labeled 'single thread IPC' while actually running two process copies per physical core, 352 across Vera's 176 cores and 512 across EPYC's 256, without disclosing how a single-thread figure was derived from that fully loaded setup. NVIDIA also attributes Olympus's IPC lead to four counter ratios, up to 2.3x more branch predictions, 3.5x more taken branches, 2.4x more instruction-fetch operations and 4.3x more backend operations per cycle, which the authors call impossible to audit without the underlying PMU event definitions, raw counts and clock frequencies, noting an Arm instruction is not directly comparable to an x86 one. Their conclusion: the IPC advantage over AMD's Turin chips may be real, but the whitepaper's charts do not provide enough detail to show it.

The memory section holds the whitepaper's strongest result and, per the authors, its weakest attribution. NVIDIA's own charts show Vera reaching roughly 1.1 TB/s against a dual-socket EPYC 9755 system that levels off near 400 GB/s, or 12.7 GB/s per core against 3.1 GB/s for the AMD chip. The authors' own testing of Turin does not match this: they measured about 570 GB/s from its 12-channel DDR5-6400 memory subsystem, about 93% of AMD's stated 614 GB/s theoretical limit, comparable to the roughly 92% of its own 1.2 TB/s theoretical limit that NVIDIA's measured 1.1 TB/s represents for Vera. Recalculated against that 570 GB/s figure, Vera's total bandwidth lead falls from the whitepaper's implied nearly 3x to about 1.9x, and its per-core lead from 4.1x to roughly 2.8x; against the EPYC 9575F, the SKU AMD actually markets for AI head nodes, the per-core gap narrows further to about 40%. The authors conclude Vera's edge comes mainly from having about twice the peak bandwidth per socket and fewer cores sharing it, not from Turin using its own bandwidth poorly, which weakens the whitepaper's repeated attribution of the advantage to Vera's monolithic die: a chiplet-based EPYC 9755 reaching about 93% of its own theoretical ceiling is not obviously held back by its chiplet topology in this case. They add that the comparison aged quickly regardless: AMD launched its 6th generation EPYC two days after NVIDIA's whitepaper, including the 96-core EPYC 9686F, whose top MRDIMM-12800 configuration gives that new platform more theoretical bandwidth than Vera, in total and per core, depending on SKU.

On a PageRank graph benchmark, NVIDIA reports a 2.6x advantage over EPYC 9755, with Vera's performance scaling almost linearly as core count rises to 32 while EPYC's own gain flattens to roughly a 10x increase by that point, which NVIDIA attributes to the monolithic die, its coherent fabric, memory bandwidth and graph prefetcher. The authors note the scaling chart stops at 32 cores even though the tested chips have 88 and 128 cores per socket, and that NVIDIA does not disclose the GAP Benchmark Suite variables used, making the 2.6x result likely irreproducible. A ClickHouse comparison, where Vera led across three passes over a 100 million row dataset, draws on a published Phoronix result and reads as more credible to the authors, though still selective for excluding the EPYC 9575F. The reinforcement-learning claim in Figure 24, 'Vera drives 1.8x for RL training,' is illustrated only by a row of small squares, with no model, environment, hardware allocation, framework, batch size, power measurement, repetition count or error bar given; the authors call it not a bad benchmark, simply not a benchmark at all.

The authors sum up that their view of Vera is more positive than their view of the Vera whitepaper. Olympus looks like a genuinely strong core, with a wide decoder, large private caches, value prediction and graph-aware prefetching, and early independent testing backs at least some of NVIDIA's numbers. But they describe the competitive argument as much shakier: it mischaracterizes x86 SMT, turns an optional NUMA configuration into a supposed default burden, relabels standard CPU tests as agentic workloads, hides a 3% two-socket throughput lead behind 1.8x per-core bars, compares undefined cross-ISA counters, credits a memory-interface win to monolithic design over evidence that says otherwise, and presents an unlabeled illustration as performance data. They call for independent reviewers to get unrestricted production hardware, with frequency, package power and wall power monitoring enabled and SMT toggled on and off, so any future comparison of Vera against x86 rivals can be checked rather than taken on faith.

Key facts

  • NVIDIA's 45-page Vera whitepaper describes an 88-core Olympus-based server CPU; Phoronix's independent testing found it 10% faster than a 5 GHz EPYC 9575F, 1.55x a Xeon 6980P, and 1.63x Grace.
  • The whitepaper's Figure 5 contrasts x86 SMT with Vera's 'Spatial Multithreading' in a way Chips and Cheese calls misleading: NVIDIA's own text credits the design with determinism and isolation, not speed, while its diagram implies traditional SMT wastes resources that per-cycle thread selection can actually reuse.
  • NVIDIA labels four standard SPEC CPU 2026 tests, CPython, GCC, LLVM and Cppcheck, as 'agentic benchmarks' and highlights a 1.7x to 1.8x per-core edge, while the full two-socket SPECrate total shows only a 3.0% system-throughput advantage (925 vs 898) because Vera uses 176 cores against EPYC's 256.
  • NVIDIA's own chart shows AMD's Turin chip capping near 400 GB/s of memory bandwidth, but the authors measured about 570 GB/s from a Turin system themselves, cutting Vera's claimed 'nearly 3x' total bandwidth lead to about 1.9x and its per-core lead from 4.1x to roughly 2.8x.
  • The whitepaper's Figure 24, claiming Vera drives a 1.8x reinforcement-learning speedup, shows only a row of unlabeled squares with no model, hardware or methodology disclosed, which the authors say 'simply is not a benchmark at all.'

Why it matters

Vera is NVIDIA's first server CPU, an Arm chip built to compete with x86 datacenter processors from AMD and Intel, and its 45-page whitepaper is the primary document early buyers, reviewers and the press will read before independent hardware is widely available. Chips and Cheese's critique separates two claims that often get merged when a new chip launches: whether the silicon is fast, and whether the marketing built around it is honest. The authors conclude the silicon looks genuinely strong, backed by outside testing, but that NVIDIA's own comparisons make its lead over rivals look larger and more settled than the disclosed data supports, through a misleading SMT diagram, a cherry-picked NUMA baseline, relabeled SPEC tests, unauditable IPC counters, a memory-bandwidth figure the authors could not reproduce, and a reinforcement-learning chart with no methodology behind it at all.

Who it affects

Datacenter buyers and system integrators weighing Vera as an Arm alternative to AMD's EPYC or Intel's Xeon lines are the most direct audience, since whitepaper claims shape early shortlists before independent benchmarks exist. NVIDIA's own credibility is at stake as it expands from GPUs into general-purpose server CPUs, a category where AMD and Intel have decades of established benchmarking practice. AMD is affected most directly: the whitepaper's headline bandwidth and PageRank comparisons run against its EPYC 9755 and Turin platform, and the authors show AMD's newly launched 6th generation EPYC chips, including the 96-core EPYC 9686F, already offering more theoretical memory bandwidth than Vera itself at top MRDIMM speeds, undercutting the whitepaper's comparison within days of its release. Reviewers and press who cite whitepaper multipliers without independent testing, and engineers who might tune software for Vera's 'Spatial Multithreading' or single NUMA domain per socket, are also affected by which of NVIDIA's framing choices hold up.

How to use it

Vera has no announced price and remains pre-production, tested publicly for only one day by Phoronix under conditions NVIDIA controlled, so there is nothing yet to buy or benchmark independently at scale. For anyone reading the whitepaper itself, the authors' practical advice is to discount the multipliers that come with no disclosed methodology, the 1.8x reinforcement-learning figure, the 2.6x PageRank result built on a scaling chart that stops at 32 cores, and the undefined IPC counter ratios, and to anchor instead on the few numbers that are reproducible: Phoronix's independently run geomean (10% above a 5 GHz EPYC 9575F, 1.55x a Xeon 6980P, 1.63x Grace) and the full-suite SPECrate total (a 3.0% two-socket system advantage over EPYC 9755, or about 50% per core). The authors' own request is for NVIDIA to give independent reviewers unrestricted production hardware, with frequency, package power and wall power monitoring enabled and SMT toggled on and off, so any future comparison can be checked rather than taken on faith.

How solid is it

The critique's strongest point is that the authors ran their own test rather than only reading NVIDIA's charts: they measured about 570 GB/s of memory bandwidth from a Turin (EPYC) system, about 93% of AMD's stated 614 GB/s theoretical limit, directly contradicting NVIDIA's own plotted figure of Turin capping near 400 GB/s and forcing a recalculation of Vera's bandwidth lead from a claimed 'nearly 3x' down to about 1.9x. NVIDIA's Phoronix-run benchmark is also independently sourced, though NVIDIA chose the workload scope and disallowed frequency or power monitoring on a pre-production system tested for one day. Elsewhere the evidence is thinner: the IPC counter ratios come with no PMU event names, definitions or sampling intervals; the NUMA latency heatmap has no core identities, distribution or measurement procedure; the PageRank scaling chart stops at 32 cores despite testing 88 and 128-core chips, without disclosing the GAP Benchmark Suite variables used; and the reinforcement-learning figure discloses no model, hardware, framework or error bar at all. One point favors NVIDIA: the authors confirm the SPEC results are correctly labeled as estimates, since production Vera hardware was not yet available when they were run.

Risks and caveats

The comparison aged quickly on its own terms: AMD launched its 6th generation EPYC two days after NVIDIA's whitepaper, including the 96-core EPYC 9686F, whose top MRDIMM-12800 configuration offers more theoretical memory bandwidth than Vera, in total and per core, depending on SKU. The piece includes no response from NVIDIA to this specific critique, and no pricing or general-availability date is given anywhere for Vera or the comparison chips, so procurement decisions cannot rest on this document alone. Readers should also weigh that every number favorable to Vera in the whitepaper passed through configurations NVIDIA chose (permitted Phoronix workloads, a 32-core PageRank scaling cutoff, an unaudited IPC methodology), while the one clear factual correction in the piece, the Turin bandwidth figure, came from the authors' own separate testing rather than from NVIDIA revising its claims.

“None of that makes Vera slow, it simply makes NVIDIA's proof smaller than NVIDIA Marketing's prose.”

— George Cozma and Chester Lam, Chips and Cheese