Glonce

AMD Zen 6 and Zen 6c: Chips and Cheese maps the changes from Zen 5

infrastructureThe Glonce editorsHacker News🔥76Glonce rating76Impact62Novelty68Relevance100Surprise45Players78Credibility85
AMD Zen 6 and Zen 6c: Chips and Cheese maps the changes from Zen 5

Chips and Cheese has published a microarchitecture analysis of AMD's next-generation Zen 6 core family, covering the classic Zen 6 core and the dense Zen 6c, and comparing both with Zen 5. The article's first impression is that Zen 6 is a natural evolution of Zen 5, with many out-of-order structures enlarged. Digging deeper, it says AMD heavily reworked several parts of the core, which reminds the author of the changes from Zen 1 to Zen 2. The integer schedulers stand out: they return to a layout reminiscent of Zen 3 and Zen 4.

Branch prediction: Zen 5 had the best direction predictor of any core the site has measured, and Zen 6 seemingly builds on it. Both cores hit the wall at about the same place. Past it, the predictor is guessing at random data, so time per branch mostly reflects recovery from a wrong guess. That plateau is roughly 3.5 to 4 ns of extra time per branch on Zen 5 and roughly 3 to 3.5 ns on Zen 6, which the author reads as AMD reducing mispredict latency. Zen 6 can also do two branches per cycle within the L1 instruction cache; beyond the L1i it falls to one per cycle. Compared with Zen 5, Zen 6 appears to have focused on BTB speed rather than capacity, and its accuracy is very similar to Zen 5's while being faster.

Fetch: Zen 6 keeps the dual decode cluster layout introduced in Zen 5, but where a single Zen 5 thread could effectively use only one cluster, a single Zen 6 thread can now use both. Outside the L1i, instruction-side behavior looks very similar to Zen 5.

Execution engine: Zen 6 brings back Zen 4's NOP pairing, retiring up to 16 NOPs per cycle. With the same six ALUs it sustains 5.96 64-bit adds per cycle against Zen 5's 5.25. AMD cut integer multiply units from three to two, and PDEP and PEXT throughput falls from three instructions per cycle to two; according to AMD, Zen 5's third multiply unit did not justify its area cost. The floating-point units are unchanged, still handling two 512-bit FADDs, FMULs or FMAs per cycle. VNNI doubles from two units to four, and the 512-bit VNNI test goes from 1.99 to 3.88 instructions per cycle, with Zen 6c matching it. The article notes VNNI helps with the inner loop of quantized inference and with video filters. Zen 5 could perform four loads per cycle but only two could be vector loads; Zen 6 raises 256-bit vector loads to four per cycle on both cores while 512-bit loads stay at two, so both widths reach 128 bytes per cycle. That matters, the article says, because most shipped vector code still targets AVX1/2.

Where Zen 6 and Zen 6c split: in past generations the classic and dense cores were functionally identical in architecture, differing mainly in cores per CCD and L3 per core. That has changed. The differences begin after micro-op dispatch and seemingly end after the load queue, and several out-of-order structures are larger on Zen 6c. The reorder buffer grows from 576 to 640 entries, the integer register file from 288 to 352, the vector scheduler from 138 to 180, and the load queue from 280 to 330. The author concludes that AMD is specializing the two designs: Zen 6 tuned for high frequency, Zen 6c for tolerating higher memory latency.

Cache: Zen 6 and Zen 6c use 12-core and 32-core CCDs, both with 4 MB of L3 per core, giving 48 MB and 128 MB per CCD. L3 latency rises from about 47 cycles on Zen 5 to 55 cycles on Zen 6 and 66 cycles on Zen 6c; larger caches and more mesh stops likely contribute. In nanoseconds Zen 6's higher clock hides most of it: 10.7 ns versus 10.3 ns on the Zen 5-based EPYC 9355P, while Zen 6c's lower clock and larger CCX put it at 16.4 ns. Zen 6 also fixes Zen 5's odd L2 bandwidth behavior, where a core pulled only about 42 bytes per cycle across most of the L2; the read path now reliably delivers 64 bytes per cycle. Store-to-load forwarding is seemingly unchanged from Zen 5, and it is where Zen 6 and Zen 6c behave the same again: a 32-bit load from the same address as a 64-bit store completes with effectively zero latency, loads fully contained in the store take 7 cycles, and partial overlaps cost 14.

SPEC CPU 2026: the figures are the site's own estimated single-threaded results. The EPYC 9686F roughly matches the Ryzen 9 9950X3D2 in integer and beats it in floating point; at a matched 4.1 GHz it leads by about 4% in integer and 11% in floating point, despite the X3D part's much larger L3. The EPYC 9996 roughly matches the previous-generation EPYC 9575F in single-threaded performance despite lower clocks and four times as many cores (5.25 versus 5.13 integer, 8.99 versus 9.01 floating point, about 900 MHz slower). It edges out NVIDIA's Vera in integer and leads it by about 20% in floating point. The 9686F finishes about 18% ahead of the 9996 in both suites (6.20 versus 5.25 integer, 10.6 versus 8.99 floating point), though the 9996 edges it in 721.gcc and 765.roms.

Top-down breakdowns explain the gap. Core-bound integer subtests look almost identical on both chips, but memory-heavy ones differ: moving from the 9996 to the 9686F, backend memory stalls rise from 37.9% to 50.0% of pipeline slots in 729.abc, from 19.0% to 34.1% in 723.llvm and from 24.8% to 33.2% in 708.sqlite. In floating point they rise from 42.5% to 55.3% in 765.roms, from 60.9% to 67.6% in 749.fotonik3d and from 17.8% to 33.8% in 782.lbm. With the 9686F run at 4.1 GHz to match the 9996, the picture flips: it scores 4.92 integer and 8.64 floating point, which the article reads as Zen 6c being about 6.7% ahead per clock in integer and 4% in floating point. Memory stalls are still larger on the 9686F, and frontend latency stalls are much larger in big-codebase tests: 35.2% versus 16.6% in 727.cppcheck and 25.8% versus 10.0% in 721.gcc. Since both designs share a frontend, the author thinks this most likely reflects the cache and memory hierarchy, with Zen 6c's 128 MB L3 serving more requests than Zen 6's 48 MB.

In the closing section the author says Zen 6 brings a generational uplift over Zen 5, and calls the split between Zen 6 and Zen 6c the more interesting change: the shared foundation is clear, but the differences make the choice between them depend more on workload behavior. The estimated results also show the EPYC 9686F ahead of the Zen 5-based EPYC 9575F by about 21% in integer and 18% in floating point.

Key facts

  • Zen 6 and Zen 6c differ in the out-of-order engine for the first time in a classic/dense pair: reorder buffer 576 vs 640 entries, integer register file 288 vs 352, load queue 280 vs 330.
  • VNNI units double from two to four, taking the 512-bit VNNI test from 1.99 to 3.88 instructions per cycle; integer multiply units drop from three to two.
  • The mispredict plateau falls from roughly 3.5 to 4 ns per branch on Zen 5 to roughly 3 to 3.5 ns on Zen 6, and a single thread can now use both decode clusters.
  • In estimated SPEC CPU 2026 single-thread results, the EPYC 9686F leads the EPYC 9996 by about 18% in both suites at stock clocks; at a matched 4.1 GHz the 9996 is ahead per clock.
  • L3 latency grows from about 47 cycles on Zen 5 to 55 on Zen 6 and 66 on Zen 6c, but Zen 6's higher clock keeps it at 10.7 ns vs 10.3 ns on the EPYC 9355P.

Why it matters

The article argues Zen 6 is not a simple Zen 5 refresh. It compares the scale of the rework to Zen 1 to Zen 2, with integer schedulers returning to a Zen 3 and Zen 4 style layout. The bigger novelty, in the author's view, is that the classic and dense cores no longer share the same architecture: in past generations they were functionally identical apart from core count and L3 per core, and with Zen 6 the out-of-order structures differ. Zen 6 appears tuned for high frequency, Zen 6c for tolerating memory latency.

Who it affects

Mainly people who follow or evaluate server and high-end desktop CPUs, since the SPEC CPU 2026 estimates are for EPYC parts and the Ryzen 9 9950X3D2 serves as a comparison point. The VNNI doubling is relevant to anyone running quantized inference or video filters on CPU, as the article points out. The wider vector load change touches the AVX1/2 code that the article says most shipped vector software still uses.

How to use it

This is an analysis, not a product to adopt. The visible text gives no release date, launch window or pricing for Zen 6 or Zen 6c products. The practical takeaway the author offers is that the choice between Zen 6 and Zen 6c depends more on workload behavior: frequency-sensitive work favors Zen 6, while latency-heavy, memory-bound work may suit Zen 6c's bigger structures and 128 MB CCD L3.

How solid is it

The numbers come from the site's own microbenchmarks and top-down profiling on named parts (EPYC 9686F, EPYC 9996, EPYC 9575F, EPYC 9355P, Ryzen 9 9950X3D2). The SPEC CPU 2026 figures are described as estimated single-threaded results, not official submissions. One detail comes from AMD: that Zen 5's third integer multiply unit did not justify its area cost. Many explanations are hedged by the author, using words like seemingly, appears and likely.

Risks and caveats

Several conclusions are inferences. The L3 latency rise is attributed only to likely causes (larger caches, more mesh stops). The frontend stalls on the 9686F are said to most likely reflect cache and memory hierarchy differences. The per-clock edge for Zen 6c is measured with different core counts, CCD sizes and L3 capacities, so it mixes core design with cache design. The chips also run at different clocks at stock, so the 18% lead of the 9686F is a clock-driven result and flips at matched 4.1 GHz.

“Zen 6 appears tuned for high frequency, while Zen 6c has more capacity to tolerate comparatively high memory latency.”

— Chips and Cheese, AMD's Zen 6 Family: Feeding the Beast