Jane Street launches ASIC reverse-engineering puzzle
Jane Street has published a new puzzle for its hardware and software community, following an earlier one that gave participants a complete neural network and asked them to figure out what it did. This time the firm has designed an ASIC (an application-specific integrated circuit) and is releasing only its final mask: the metal, routing and active-transistor layers that make up the physical layout, along with some sample inputs and outputs. Nothing in the file is labeled.
Solvers first have to recover a netlist, the logical description of gates and connections, from the raw layout. Then they must work out the circuit's true purpose. The puzzle within the puzzle comes next: once the chip's function is understood, participants use it to derive the specific output it is looking for and submit a final string value as their answer. Jane Street notes the design includes a section used to generate the output that does not affect a separate success signal, which solvers can ignore during the initial reverse-engineering steps, and that a few Easter eggs are hidden in the circuit and the accompanying repository, including in parts not needed to solve the main puzzle.
For anyone who has never opened a chip layout file (a GDS) before, Jane Street is also providing a warm-up: a simple binary adder together with its Verilog source, gate-level netlist and resulting GDS, meant to let solvers learn how a circuit maps onto a layout and test their tools before tackling the real puzzle. All the tooling needed is free and open source, built on an open-source process design kit (PDK) and viewers such as KLayout or Magic VLSI.
The firm sets explicit rules on AI use: participants must not feed the puzzle files directly into an AI tool or use AI to generate their writeups, though using AI to write helper scripts or code is allowed, as is using AI to work through the warm-up puzzle specifically. Collaboration with friends is fine, but Jane Street asks that solvers not post spoilers or a full writeup online before submissions close. Submissions close on September 4th, 2026. The most interesting writeups and techniques will be featured in a follow-up post, with swag going to favorite solutions; solvers who publish a solution after the deadline can email Jane Street to be considered for inclusion in that post.
Jane Street frames the puzzle as a warm-up for something bigger: later this year it plans to launch a competition where, instead of reverse engineering a given chip, entrants design their own, and the most interesting entries will actually get fabricated so their creators can test them in real life. The firm says its hardware team designs FPGAs and ASICs that run some of its trading systems, and that this kind of puzzle, staring at gates, timing reports and waveforms to work out what is really happening, reflects its day-to-day work.
Key facts
- Jane Street released only the final GDS mask (metal, routing and transistor layers) of a chip it designed, with no labels and no source code, and sample inputs and outputs to work from.
- Solvers must recover a netlist from the layout, determine the chip's function, then use it to produce a hidden final string as their answer.
- A free warm-up puzzle (a binary adder with Verilog source, netlist and GDS) is provided to help newcomers learn to read chip layouts before attempting the main puzzle.
- Feeding the puzzle files directly into an AI tool or using AI to generate writeups is banned, but AI-written helper scripts are allowed, as is using AI on the warm-up puzzle.
- Submissions close September 4th, 2026; Jane Street plans a follow-up competition later this year where entrants design their own chips, with the best entries actually fabricated.
Why it matters
It is a second entry in a running series after an earlier neural-network puzzle, and it goes a level deeper: instead of handing over a labeled design, Jane Street gives only the physical mask, forcing solvers to reconstruct the logic from geometry alone before they can even start reasoning about what the chip does.
Who it affects
Hardware engineers, chip-design hobbyists and reverse-engineering enthusiasts who want a concrete, self-contained exercise in reading GDS layouts; it also doubles as recruiting content, pointing toward Jane Street's FPGA and ASIC internships and full-time hardware roles, its open-source Hardcaml libraries, and its visiting-researcher and graduate-fellowship programs.
How to use it
The puzzle files, the warm-up adder example, and submission instructions are all in Jane Street's puzzle repository, linked from its blog post; everything needed is free and open source, built on an open-source PDK with viewers like KLayout or Magic VLSI. Submissions are due by September 4th, 2026, with a brief writeup of the solving method, and go to asic-puzzle@janestreet.com for questions (no hints given).
How solid is it
This is a firsthand announcement from Jane Street itself on its own blog, describing a puzzle it built and is running directly, so the mechanics and rules described here are as stated by the source; the ASIC's actual function and the final answer are deliberately not disclosed, since that is the content of the puzzle.
Risks and caveats
The puzzle explicitly forbids feeding its files into AI tools or using AI to write up a solution, and asks solvers not to post spoilers or full writeups before the September 4th deadline; the firm gives no hints beyond email support, and no details on the swag prizes or the later chip-design competition's exact launch date are provided yet.
“The GDS is, in a very real sense, the chip. Everything the circuit does is in there. The tricky part: nothing is labeled!”
— Jane Street