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Meta's MTIA 400 chip trains AI models and serves ads

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Meta's MTIA 400 chip trains AI models and serves ads

Meta detailed the MTIA 400 (Meta Training and Inference Accelerator) at the Hot Chips semiconductor conference this week, according to a report by The Register's Tobias Mann. It is Meta's first generative AI accelerator built primarily for large language model training. Unlike Meta's earlier custom chips, which were built to serve ads, or OpenAI's inference-focused Jalapeno chips, the MTIA 400 is designed to also run the deep learning recommender model (DLRM) inference workloads that power Meta's ad business, pairing two very different job profiles on one part: LLM training is compute-intensive, while DLRM inference is mostly memory-bound.

On architecture, the MTIA 400 uses a multi-die design: two compute dies, two I/O dies, and an SoC die that handles host connectivity and workload orchestration. The compute chiplets are built on a 3nm process, presumed by the author to be TSMC's, with a 6x8 grid of processing elements each; combined, the two chiplets output 12 petaFLOPS of MXFP4 compute at 1.7 GHz. That makes the MTIA 400 about 20 percent faster than Nvidia's top specced Blackwell accelerators at the higher precisions commonly used for training, at roughly the same power draw, though it is between 3x and 3.3x slower than Nvidia's next generation Rubin chips and AMD's Instinct MI455X. On memory, eight 36 GB HBM3e stacks give the chip 288 GB of capacity and about 9.2 TB/s of bandwidth: roughly 15 percent faster than Nvidia and AMD's last generation parts, but less than half the bandwidth of their newest GPUs, which the author says explains why Meta positions the part for training rather than inference.

A pair of I/O chiplets provide 1.2 TB/s of chip to chip bandwidth over RDMA; the transport technology is not confirmed, though the author guesses Ethernet given the apparent involvement of Broadcom, whose XPU IP the chip was almost certainly built with. At the system level, each compute blade carries four MTIA 400 accelerators linked via a PCIe switch to an x86 CPU and a scale out NIC, and a single rack holds 18 compute blades plus eight switch blades for 72 accelerators in one unified domain. Meta has not disclosed how large a full training cluster can scale; its Hot Chips slides state only "multi-thousand accelerator scaling."

Meta also laid out a roadmap. The MTIA 450, disclosed back in March, doubles the chip's memory bandwidth, presumably by swapping HBM3e for HBM4, and is expected to enter production next year to handle inference for Meta's LLM based recommender models. The MTIA 500 is slated for 2027 (probably the second half, by the author's estimate), adding another 50 percent of memory bandwidth and doubling the number of compute chiplets. Despite MTIA's expanding role, the author notes that Meta's in-house silicon probably will not replace AMD or Nvidia GPUs any time soon: those remain better suited to LLM inference and are almost certainly what Meta Superintelligence Labs uses to train frontier models such as Muse Spark.

Key facts

  • The MTIA 400's two compute chiplets output 12 petaFLOPS of MXFP4 compute at 1.7 GHz, each built on a 6x8 grid of processing elements.
  • It runs about 20 percent faster than Nvidia's top specced Blackwell accelerators at higher training precisions while drawing similar power, but is 3x to 3.3x slower than the next generation Nvidia Rubin and AMD Instinct MI455X.
  • Memory comes from eight 36 GB HBM3e stacks: 288 GB total and about 9.2 TB/s of bandwidth, roughly 15 percent faster than Nvidia and AMD's last generation chips but under half the bandwidth of their newest GPUs.
  • A rack packs 18 compute blades (four MTIA 400 chips each) and eight switch blades for 72 accelerators in one unified domain, linked at 1.2 TB/s chip to chip over RDMA.
  • Meta's roadmap adds the inference focused MTIA 450 (double memory bandwidth, production next year) and the MTIA 500 (2027, another 50 percent bandwidth, double the compute chiplets).

Why it matters

The MTIA 400 is Meta's first custom accelerator aimed squarely at training generative AI models rather than only serving ads, and it is built to do both jobs on one chip. That is unusual: LLM training is compute heavy while the DLRM inference behind ad recommendations is mostly memory bound, so combining them trades some efficiency for the ability to keep expensive silicon busy on Meta's most profitable workload when it is not training. It also marks a step up in Meta's vertical integration in AI hardware at a time when the company is spending heavily on compute, and the chip's raw numbers put it ahead of Nvidia's current Blackwell generation on some training measures, even as it trails the upcoming Rubin and Instinct MI455X parts.

Who it affects

This is internal Meta infrastructure, not a product sold externally, so the direct audience is Meta's own AI and ads engineering teams plus the hardware ecosystem around them: Broadcom, whose XPU IP the chip was almost certainly built with, and rivals Nvidia and AMD, whose GPUs the author says Meta Superintelligence Labs is still almost certainly using to train frontier models like Muse Spark. Consumers are not directly affected; the chip's most visible consumer facing effect would be through faster or cheaper ad serving and, eventually, LLM based recommender systems.

How to use it

There is nothing to use yet outside Meta: no pricing, no external availability, and no confirmed shipping date for the MTIA 400 itself were disclosed at Hot Chips. What was shared is a roadmap. The inference optimized MTIA 450 was disclosed back in March and is expected to enter production next year, doubling memory bandwidth by presumably moving from HBM3e to HBM4. The MTIA 500 is slated for 2027, probably in the second half by the author's estimate, adding another 50 percent of memory bandwidth and doubling the number of compute chiplets.

How solid is it

The figures come from Meta's presentation and slides at the Hot Chips conference, reported firsthand by The Register's Tobias Mann rather than from an official Meta press statement. The hardware specifications (die count, compute throughput, memory capacity and bandwidth, rack configuration) are described as disclosed at the event. Several surrounding claims are explicitly the author's informed inference rather than Meta confirmed fact: that Broadcom's XPU technology was used, that the compute chiplets are fabricated on a 3nm process at TSMC, and that Ethernet is the likely transport for the chip to chip RDMA link.

Risks and caveats

No pricing is given for the MTIA 400, 450, or 500, and no general availability or shipping date is confirmed for the MTIA 400 itself. The transport technology behind the 1.2 TB/s RDMA link is unconfirmed, only guessed at. Meta has not disclosed how large a full training cluster built from MTIA 400s can scale beyond the phrase "multi-thousand accelerator scaling" on its slides, and the article names no specific ad recommender system or DLRM model the chip will actually run.

“multi-thousand accelerator scaling”

— Meta, Hot Chips presentation slides