Micron drops 4F² DRAM after two decades, sticks with 6F² as rivals push ahead

Micron has told the market it is giving up on 4F² DRAM. At a webinar on a Wednesday (the source gives no calendar date) where it laid out its future roadmap, the company said that despite "over two decades" of research it will stay with the 6F² cell geometry for the foreseeable future. The decision comes as all three of its competitors, Samsung, SK hynix and CXMT, are moving ahead with 4F² designs. CXMT in particular claims it will have 4F² RAM in server DDR5 RDIMMs by the end of the year.

Some background from the article: 6F² and 4F² are cell geometries, not process nodes. They describe the shape and layout of a DRAM cell, not its physical size, which comes from the combination of layout and process node. Each DRAM cell is a transistor plus a capacitor, so it does not scale like logic, and vendors mark node changes with labels such as 1γ and 1δ (gamma and delta). Moving from 6F² to 4F² has long been the holy grail, offering a theoretical 33% density improvement.

Micron's President and CTO, Scott DeBoer, says DRAM density is ultimately set by the spacing the capacitors require, not by the nominal cell footprint. On paper, shrinking from 6F² to 4F² looks like an easy win, but according to DeBoer it does not gain much in density and it drastically increases cost and complexity. He noted that Micron "invented" 4F² and had been trying to work out how to commercialize it for "over two decades" before discarding it.

What Micron will do instead is scale 6F² DRAM aggressively. Its roadmap notes that high-density 1δ memory is ramping yields, that 1-ε (epsilon), featuring advanced wafer bonding, is in development, and that it sees "ζÅ" (zeta-Angstrom) and "ηÅ" (eta-Angstrom) as its future for planar DRAM. The real future, according to Micron, is 3D DRAM: memory in which multiple physical layers of DRAM storage cells are stacked vertically. That differs from the wafer bonding in the roadmap, which stacks DRAM on top of logic.

The article's author explains why this is hard. Flash memory has been built in 3D for more than a decade, but flash uses simple charge-trap transistors that stack like floors in a skyscraper. DRAM cells are dynamic: each bit needs a delicate, high-aspect-ratio capacitor paired with a transistor that leaks charge. Turning those tall capacitors sideways and scaling them vertically without thermal crosstalk or signal destruction requires a total overhaul of the basic DRAM architecture. The author says that transition won't happen overnight, but that 3D DRAM is where the industry is headed as 2D scaling hits its physical limit.

The author's own assessment: in the short term Micron could face challenges if competitors can economically manufacture 4F² memory at scale, and the company is making a big strategic wager that 4F² will prove a costly, short-lived detour. If Samsung, SK hynix or CXMT spend billions on vertical-channel transistors and then hit an early wall with capacitor scaling, Micron will look smart for skipping it. By squeezing 6F² lithography with High-NA EUV, advanced materials and wafer-on-wafer bonding through the zeta and eta eras, the author says Micron hopes to save cash and engineering effort to be first when true monolithic 3D DRAM becomes economically viable. That is the author's interpretation, not a stated Micron quote.

Key facts

Micron says it will not bring 4F² DRAM to market and will stay with 6F² cells for the foreseeable future, after "over two decades" of research.
Samsung, SK hynix and CXMT are all moving ahead with 4F² designs; CXMT claims 4F² RAM in server DDR5 RDIMMs by the end of the year.
CTO Scott DeBoer says 4F² gains little density, since capacitor spacing sets density, while drastically raising cost and complexity. The theoretical gain is 33%.
Micron's roadmap: 1δ ramping yields, 1-ε with advanced wafer bonding in development, then ζÅ and ηÅ for planar DRAM.
Micron says the real future is 3D DRAM, with storage cells stacked vertically, which the article says needs a total overhaul of DRAM architecture.

Why it matters

4F² has been the long-awaited next step for DRAM cell geometry, with a theoretical 33% density gain over 6F². The company that says it invented it is now walking away, while its three rivals press on. If Micron is right that capacitor spacing, not cell footprint, sets real density, the other three may spend heavily for a small gain. If it is wrong, it may trail in the short term. The article frames it as a strategic wager on 3D DRAM.

Who it affects

Micron and its three competitors, Samsung, SK hynix and CXMT, are the direct players. The article also touches buyers of server memory, since CXMT claims 4F² RAM in server DDR5 RDIMMs by the end of the year. The article says nothing more specific about customers.

How to use it

This is a roadmap signal, not a product you can buy. Treat it as a way to read the memory vendors' plans: Micron on 6F² scaling (1δ now, 1-ε in development, then ζÅ and ηÅ) and then 3D DRAM, versus its rivals' 4F² designs. Watch whether CXMT delivers its year-end 4F² RDIMM claim.

How solid is it

The decision comes from Micron's own webinar, and the article attributes the density and cost arguments to CTO Scott DeBoer. The 33% density figure is theoretical. No real density, cost or yield figures are given for 4F² versus 6F². CXMT's year-end claim is a claim, with no verification given. The webinar's date is given only as "Wednesday". The interpretation of Micron's motives and the scenario of rivals hitting a capacitor scaling wall are the author's own.

Risks and caveats

In the short term Micron could face challenges if rivals can economically make 4F² memory at scale, as the author puts it. 3D DRAM is described as needing a total overhaul of the DRAM architecture and as not coming overnight; no timescale is given for it or for the 1-ε, ζÅ or ηÅ steps. The article gives no capital spending figures for Micron or its rivals.

“it's throwing in the towel and sticking to 6F² for the foreseeable future”

— HotHardware, describing Micron's decision on 4F² DRAM