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Nvidia Vera CPU: 88 custom Olympus cores challenge Intel, AMD

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Nvidia Vera CPU: 88 custom Olympus cores challenge Intel, AMD

Nvidia has, for the first time, directly challenged Intel and AMD's dominance of the CPU market. With Vera, the follow-on to its Grace CPU, the company is offering a standalone chip that hyperscalers can deploy independent of Nvidia's GPUs: Alibaba, ByteDance, Meta, Oracle, CoreWeave, Lambda, Nebius and NScale have already signed up to deploy it in their clouds. A single Vera CPU packs 88 custom Armv9.2 cores, 176 threads, and support for up to 1.5 TB of LPDDR5X memory.

The Register's deep dive draws on a whitepaper Nvidia released late last month, the first detailed look at the chip's internals. Nvidia is aiming Vera at two workloads: as the AI head node managing GPUs in its upcoming Vera Rubin systems, and, more contentiously, as a host for AI agents, which, unlike the large language models that power them, do not run on GPUs.

Architecturally, Vera's 88 cores sit on a single monolithic compute die, which The Register understands is fabbed on TSMC's 3nm process, surrounded by separate chiplets: eight LPDDR5X memory controllers and two I/O dies, one for PCIe 6.4 and CXL 3.1, another dedicated to Nvidia's NVLink Chip-to-Chip interface. Nvidia argues the monolithic design improves core-to-core bandwidth and latency versus chiplet-based rivals; the overall package design echoes Amazon's Graviton 4, which similarly pairs a monolithic compute die with disaggregated I/O and memory silicon.

Vera also comes in a dual-socket form Nvidia calls the Vera CPU Superchip, unveiled at GTC in March. It links two Vera CPUs over NVLink-C2C at 1.8 TB/s of bidirectional bandwidth for a combined 176 cores and 352 threads, fed by 16 SOCAMM2 LPDDR5X modules delivering 2.4 TB/s of aggregate memory bandwidth (1.2 TB/s per chip), roughly twice the bandwidth of AMD's Turin Epycs, launched in 2024. Nvidia's agentic AI reference design calls for cramming as many as 128 of these superchips, 256 CPUs in total, into a single liquid-cooled rack: 22,528 cores and 384 TB of memory.

Where Nvidia previously used off-the-shelf Arm cores in Grace (Neoverse V2, Neoverse V3, or Cortex X925/A725, depending on the product), Vera introduces Nvidia's own Armv9.2-compatible core, Olympus. The Register notes it is up for debate how custom the core really is: sources told the outlet it builds heavily on existing Arm IP, and its block diagram resembles a heavily modified Cortex X925. Olympus has a 10-wide decoder and dispatch, ten integer ALUs (eight simple units for basic math and two complex units handling multiplication, division, CRC and shifts), six 128-bit SVE2 vector/floating-point pipelines that also support FP8 plus a pair of vector units for crypto operations, four load units, two store units, and four dedicated branch units. Each core carries 64 KB of L1 instruction cache, 96 KB of L1 data cache and 2 MB of L2, with 164 MB of system-level cache shared and sharded across the chip.

Nvidia's headline addition is an entirely custom neural branch predictor that can explore two branches simultaneously per cycle; the company claims it delivers higher hit rates than history-based predictors, which it says suits branch-heavy workloads such as Python scripts generated on the fly by AI coding assistants. Two further mid-core features target pipeline stalls: memory renaming, which lets dependent instructions execute before a load completes when the relationship to the data can be inferred, which Nvidia says particularly benefits pointer-heavy software, graph traversal, runtime frameworks and complex object-oriented workloads; and value prediction, which "identifies stable dependency chains and predicts future values before they are produced, allowing dependent instructions to execute speculatively while correctness is verified later," which Nvidia says speeds up repetitive software patterns and sequential data processing.

Olympus also supports a form of simultaneous multithreading Nvidia calls "spatial multithreading." Rather than the conventional SMT that x86 chips have used since 2002, where two threads share one core's resources, Nvidia's version behaves more like splitting one core into two skinny cores that share a cache line; The Register compares it to multi-instance GPU partitioning applied to a CPU. The rationale, per the piece, is that AI agent sandboxes run two distinct jobs, the workload itself (say, a Python interpreter) and the container runtime handling orchestration, networking and storage, and bifurcating cores can keep the two separate for more deterministic performance. Arm has itself downplayed SMT's value for its own agentic CPU designs, despite having supported it before, in Cavium's ThunderX2 prior to Marvell's acquisition of Cavium.

All 88 cores are stitched together by Nvidia's second-generation scalable coherency fabric (SCF), delivering 3.4 TB/s of bisectional bandwidth through Coherency Switch Nodes that each connect up to two cores; the L3 cache lives inside the SCF, which is why the system-level cache is sharded across the chip rather than centralized. Vera's eight LPDDR5X controllers support SOCAMM2 modules up to 9600 MT/s, giving 1.2 TB/s of total memory bandwidth and roughly 14 GB/s per core, among the fastest in the industry today, though The Register notes rival chips shipped roughly two years earlier. By comparison, Intel's 192-core Diamond Rapids details remain pending, while AMD's upcoming 256-core Venice CPU will support 8,000 MT/s RDIMMs or 12,800 MT/s MRDIMMs (1 TB/s to 1.6 TB/s); both Intel and AMD's next-gen parts are moving to 16 memory channels, and assuming no bottleneck in AMD's GMI links, its 96-core Epycs should reach about 17 GB/s per core.

On power, Nvidia claims Vera's LPDDR5X memory subsystem draws just 30 to 40 watts under sustained load, against 100 to 200 watts for a traditional RDIMM server platform, within a chip TDP configurable between 250W and 450W; The Register speculates this may be why AMD's upcoming Epyc, codenamed Verano, is also adopting LPDDR5X. Vera is additionally among the first chips to support PCIe 6.4 and CXL 3.1, ahead of Intel and possibly AMD, with PCIe 6.0 doubling per-lane bandwidth to 64 Gbps over the prior generation.

Key facts

  • Vera is Nvidia's first standalone, fully custom CPU: 88 Armv9.2 Olympus cores, 176 threads, up to 1.5 TB of LPDDR5X memory, deployable independent of Nvidia GPUs; Alibaba, ByteDance, Meta, Oracle, CoreWeave, Lambda, Nebius and NScale have signed up to use it.
  • The dual-socket Vera CPU Superchip, unveiled at GTC in March, links two CPUs at 1.8 TB/s over NVLink-C2C for 176 cores and 352 threads; Nvidia's reference rack design packs up to 128 superchips (256 CPUs, 22,528 cores, 384 TB of memory) into one liquid-cooled rack.
  • Olympus adds a custom neural branch predictor exploring two branches per cycle, plus memory renaming and value prediction schemes aimed at cutting pipeline stalls, though The Register's sources say the core 'builds heavily on existing Arm IP' and resembles a modified Cortex X925.
  • Olympus supports 'spatial multithreading,' an SMT-like scheme that splits a core into two skinny cores sharing a cache line rather than sharing execution units simultaneously, meant to separate an AI agent sandbox's workload from its container runtime.
  • Nvidia claims Vera's LPDDR5X memory subsystem draws 30 to 40 watts under sustained load versus 100 to 200 watts for a traditional RDIMM platform, within a 250W to 450W chip TDP, and the chip is among the first to support PCIe 6.4 and CXL 3.1.

Why it matters

Vera is Nvidia's first move into the standalone CPU market, competing directly with Intel and AMD rather than shipping CPUs only bundled with its GPUs. It follows Grace and targets two workloads: acting as the AI head node that manages GPUs in Nvidia's upcoming Vera Rubin systems, and, more unusually, hosting AI agents, which run on CPUs rather than GPUs. Major cloud providers, including Alibaba, ByteDance, Meta, Oracle, CoreWeave, Lambda, Nebius and NScale, have already signed up to deploy Vera chips in their clouds.

Who it affects

Cloud providers and hyperscalers building AI agent infrastructure stand to gain a GPU-independent CPU option from the company that already dominates their GPU supply. Intel and AMD face a new direct competitor in the datacenter CPU market they have long split between them. Developers of AI coding agents may benefit from architectural choices Nvidia says are tuned for branch-heavy, pointer-heavy code, such as Python scripts generated on the fly.

How to use it

Vera is available as a single-socket chip or as the dual-socket Vera CPU Superchip unveiled at GTC in March, and can be deployed independent of Nvidia's GPUs. Nvidia's own reference rack design packs up to 128 superchips (256 CPUs) into a single liquid-cooled rack. The source gives no shipping date and no pricing for Vera CPUs or Superchips.

How solid is it

The account rests on an Nvidia whitepaper released late last month, combined with The Register's own analysis; none of the performance and power figures are independently benchmarked in the source. The Register flags a specific caveat on the 'custom' branding: unnamed sources told the outlet Olympus 'builds heavily on existing Arm IP,' and its architectural block diagram reads like a heavily modified Cortex X925 rather than a clean-sheet design. The TSMC 3nm process cited for the compute die is presented as The Register's own inference, not a confirmed Nvidia specification, and no individual Nvidia spokesperson is named in the piece.

Risks and caveats

This is a technical deep dive built on a vendor whitepaper, not an independent benchmark: the branch-predictor hit-rate claims, memory renaming and value prediction benefits, and the memory-subsystem power figures are all Nvidia's own. The Register cautions against reading too much into Nvidia's claims that spatial multithreading avoids the thread contention seen on x86, and the source does not say whether the feature is enabled by default or must be configured. Competing figures for Intel's Diamond Rapids and AMD's Venice CPUs are themselves partly unconfirmed or projected rather than shipped and measured.

“This is particularly beneficial for pointer-heavy software, graph traversal, runtime frameworks, and complex object-oriented workloads.”

— Nvidia, in its Vera/Olympus whitepaper, on the chip's memory renaming feature